To advance IC design and verification technologies in advanced nodes, the "16nm FinFET Mixed-signal Practical Workshop" will be held on June 18, 2026. Hosted by Prof. Hsin-Shu Chen, Director of NTU RTRC, this workshop features a practical sharing session by master's student Shih-Chi Lin.
The session will analyze the differences between FinFET and traditional Planar processes, explore layout practices, and introduce RC Extraction methods and flows specifically for the 16nm node. Attendees will learn how to establish a reliable post-layout simulation flow for successful tape-outs. We welcome students planning to tape out using 16nm or more advanced nodes, as well as those with practical needs in analog circuit layout and back-end verification.
(Basic knowledge of IC design, CMOS layout, and hands-on experience with EDA tools like Cadence Virtuoso and Calibre are recommended.)

【 Event Information 】
Date: Thursday, June 18, 2026
Time: 11:00 – 12:00
Venue: Room 106, EE Building 2, National Taiwan University
Host: Prof. Hsin-Shu Chen
Speaker: Shih-Chi Lin (Master's Student)
Registration：https://forms.gle/hBwcRzVeDYqLQMMn6
【 Agenda 】
11:00 - 12:00 | 16nm Advanced Node Tape-out Experience Sharing

【 Contact 】
Contact: Ms. Lu (yiwenlu@ntu.edu.tw / 02-33661858)
Organizers：MOE Advanced Node IC Design and Verification Environment Construction Project、NSTC Key Technologies and Innovative Applications for High-Performance Chips Project、Intelligent and Sustainable Biomedical Electronics Research Fund
Co-organizer： Graduate Institute of Electronics Engineering, National Taiwan University、NTU Radiation Application and Hardness Technology Research Center